In association with an increase in the degree of integration of LSI chips, there has been strong demand for a reduction in package size. Under these circumstances, various package structures have been proposed. In recent years, developments have been carried out intensively for stacking semiconductor bare chips in which through electrodes are formed and which have a double-sided electrode structure. This technique requires a through electrode structure (see Patent Document 1). However, the presently employed method of forming through electrodes requires complicated steps, including formation of openings of a silicon substrate, formation of insulation film covering the wall surfaces of the openings, and charge of low-resistance metal. As described above, the method of forming through electrodes in a semiconductor substrate and providing insulation therefor still involves problems to be solved, and there has been demand for a technique which enables formation of a double-sided electrode structure without requiring through electrodes. Meanwhile, in association with further evolution of cellular phones and digital cameras, product application of a wafer level chip size package (WLCSP), which is an electronic device package of real size, tends to be expanded further in future.
Although Patent Document 1 discloses a double-sided electrode structure in which projection electrodes are formed on a substrate, it does not contain specific disclosure regarding a method of forming the projection electrodes and a method of establishing connection. Although Patent Document 1 also discloses rewiring on the upper surface, it discloses only a conventional method for formation of rewiring in which film of low-resistance metal is formed on the upper surface through plating and is patterned by use of lithography. Therefore, the method disclosed in the document has a big problem in terms of cost.
In general, a semiconductor manufacturing process is divided into a former stage for fabricating an LSI and a latter stage for packaging the LSI. There are a few manufacturers that specialize in the latter stage but can cover the former stage. Manufacture of conventional electronic device packages, such as wafer level chip size package (WLCSP), requires a process of performing rewiring, plating of vertical wiring portions, etc. on a wafer; that is, requires facilities similar to those used in the former stage, and cannot be performed by use of only conventional facilities for the latter stage.    Patent Document 1: Japanese Patent Application Laid-Open (kokai) No. 2001-127243